Proposal ID: SEP-210510488
ICCS project ID: 63107000
Role: Coordinator
Acronym: TERIPHIC
Topic: ICT-04-2018
Type of action: IA
Call identifier: H2020-ICT-2018-2020

Fabrication and assembly automation of TERabit optical transceivers based on InP EML arrays and a Polymer Host platform for optical InterConnects up to 2 km and beyond: TERIPHIC

Duration in months: 36
Fixed keyword 1: Photonic integration, photonic integrated circuits
Fixed keyword 2: Photonics
Fixed keyword 3: Optical Communications
Fixed keyword 4: Electronics, photonics
Free keywords: Low cost Terabit transceivers, Automated photonic device assembly, Low cost photonic packaging,
Hybrid PIC, Mass manufacturing of photonic transceivers, Receiver optical subassembly100G-perlane trans

Efforts to develop optical interfaces with Terabit capacity for datacom applications have kicked off. A practical path to the
Terabit regime is to scale the current 400G modules, which are based (in the most forward looking version of the standards)
on 4 parallel lanes, each operating with PAM-4 at 53 Gbaud. Scaling these modules by adding lanes looks simple, but
entails challenges with respect to the fabrication and assembly complexity that can critically affect their manufacturability and
cost. TERIPHIC aims to address these challenges by leveraging photonic integration concepts and developing a seamless
chain of component fabrication, assembly automation and module characterization processes as the basis for high-volume
production lines of Terabit modules. TERIPHIC will bring together EML arrays in the O-band, PD arrays and a polymer chip
that will act as the host platform for the integration of the arrays and the wavelength mux-demux of the lanes. The integration
will rely on butt-end-coupling steps, which will be automated via the development of module specific alignment and
attachment processes on commercial equipment. The optical subassembly will be mounted on the mainboard of the module
together with linear driver and TIA arrays. The assembly process will be based on the standard methodologies of MLNX and
the use of polymer FlexLines for the interconnection of the optical subassembly with the drivers and the TIAs. Using these
methods, TERIPHIC will develop pluggable modules with 8 lanes (800G capacity) and mid-board modules with 16 lanes
(1.6T capacity) having a reach of at least 2 km. Compared to the 400G standards, the modules will reduce by 50% the
power consumption per Gb/s, and will have a cost of 0.3 Euro/Gb/s. After assembly, the modules will be mounted on the line
cards of MLNX switches, and will be tested in real settings. A study for the consolidation of the methods and the set up of a
pilot assembly line in the post-project era will be also made.

Lab URL: www.photonics.ntua.gr